With continuous advance of semiconductor manufacturing technology the electronic elements are shrunk smaller while their performances are greatly enhanced. The general semiconductor manufacturing process mainly aims to shrink the size of transistors to increase circuit integrated density of elements so that switch speed of the shrunk elements improves and power consumption is reduced at the same time, thereby to enhance the performance of the elements. In order to increase production yield the shrunk elements must be fabricated via etching processes and equipments with precise control.
In the technology area of DRAM reducing circuit area makes fabricating more memory chips possible with a given wafer to lower the cost. To meet this end vertical DRAM becomes the mainstream now. It can be divided into a trench capacitor structure and a stacked capacitor structure that are widely adopted in the industry. They can shrink the size of the memory and better utilize chip space to fabricate high density DRAM. For instance, U.S. Pat. No. 7,795,620 entitled “Transistor structure and dynamic random access memory structure including the same” discloses a surrounding gate transistor (SGT). It adopts the vertical transistor stacked structure to reduce wafer occupied area.
FIG. 1 illustrates a conventional vertical pillar transistor (VPT) which includes a bit line 1, a silicon substrate 2, a vertical transistor 3 and a capacitor 4. The bit line 1 is formed on the surface of the silicon substrate 2 via an ion-doping method. Although forming the bit line 1 via such a method is exempt from the process of burying metal lines by etching to simplify fabrication process and also get smaller couple noise, the bit line thus formed has impedance much greater than the one formed by the metal lines, that results in loss during signal transmission and decrease of electric charges saved in the capacitor 4. There is still room for improvement.